1. Field of the Invention
The present invention relates to a pulse generator which generates a CCD driving signal for driving a CCD and a CCD output processing signal for processing a CCD output signal (these two signals will be referred to as CCD control signals hereinafter) and, more particularly, to a pulse generator capable of accurate timing control of each signal.
2. Description of the Prior Art
The generating timings of signals necessary for driving and output signal processing of a CCD serving as the heart of an image reading apparatus are very important to obtain a high-quality image signal.
The signal generating timing relationship has conventionally been ensured by applying the delay characteristic of a gate circuit or inverter circuit, or using a relatively low-cost semiconductor delay element.
In conventional image reading apparatuses using line CCDs, CCDs of the same type (line sensors) are commonly adopted for high- to low-speed reading apparatuses, and large part of the circuit arrangement is kept unchanged. In practice, no circuits are common because of a change in the timing setting circuit.
Japanese Unexamined Patent Publication No. 5-275988 (see p. 1 and FIG. 1) discloses a pulse generating circuit which can be used as a pulse generator.
In recent years, demands have arisen for increasing the speed and resolution of image reading apparatuses. Along with this, the CCD driving speed also increases.
For example, a fixed period necessary to drive a CCD exists in a CCD output signal, and limits the effective period of the CCD output signal serving as an image signal. The effective period becomes narrower for higher-speed driving, and it becomes difficult to control the sampling timing of the CCD output signal.
FIG. 6 is a waveform chart showing an example of the waveform of a CCD output signal. FIG. 6 shows an example of the waveform for one pixel. The period during which the CCD output signal can be sampled and held as an image signal is limited to an image signal stabilization period {circle around (4)} in FIG. 6. For example, one cycle from {circle around (1)} to {circle around (5)} for a read frequency (CCD transfer signal frequency) of 20 MHz is 50 ns. A reset period+clamp period {circle around (1)} is about 20 ns at minimum due to CCD driving specifications. A field-through period {circle around (2)} is set to 0 ns by controlling the timings of a transfer clock and reset pulse in order to ensure an image stabilization period in high-speed driving at the reference level of correlated sampling. An image signal fall period {circle around (3)} is influenced by the tr and tf of the transfer clock, and must be about 15 ns in general. Similarly, an image signal rise period {circle around (5)} must be about 5 ns in general.
The remaining image signal period {circle around (4)} is tw{circle around (4)}=50−{circle around (1)}−{circle around (2)}−{circle around (3)}−{circle around (5)}=50−20−0−15−5=10, i.e., 10 ns. Even during the 10-ns period, the sample-and-hold point of a signal exists. An optimal sample-and-hold point is one at which a maximum amplitude is resultantly obtained and the noise amount minimizes. This point exists at latter part of the image signal stabilization period {circle around (4)}, but if the point comes too closer to the period {circle around (5)}, noise increases.
As described above, control of the sample-and-hold timing of a CCD output signal is critical, and becomes more critical for higher-speed driving.
For this purpose, high-speed or high-resolution image reading apparatuses have to use expensive, high-precision delay elements in order to generate CCD driving signals (CCD reset signal, CCD clamp signal, spare signal, and the like) and CCD output processing signals (sampling signal and the like) at accurate timings.
Due to variations between apparatuses, the apparatuses may not operate in a design state. Some apparatuses take an apparatus arrangement in which the delay state of a high-precision delay element is controlled using a jumper switch or the like.
CCDs of the same type are commonly adopted for high- to low-speed reading apparatuses, and large part of the circuit arrangement is kept unchanged. In practice, no circuits can be common because of a change in the timing setting circuit.